1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for sampling a valid command using an extended valid address window in a double pumped address scheme memory device.
2. Description of the Related Art
As the capacity of a memory device increases, the number of address signals for addressing memory cells increases. The address signals are provided to the memory device through address pins. In a synchronous memory device such as SRAM, command signals CMD and address signals ADDRs are input in synchronization with a clock signal CLK to the memory device, as shown in FIG. 1. The command signals CMD include signals /RAS, /CAS, /CS and /WE and the address signals ADDRs are, for example, 12 address signals A0 through A11.
To input the address signals A0 through A11 to the memory device, the 12 address signals are connected to the memory device through routing of a system board. The number of address pins of the memory device can be reduced from 12 (A0 through A11) to 6 (A0 through A5) in a double pumped address scheme. This simplifies system board design. Furthermore, internal power of a chip can be stabilized by using a power pad instead of an address pad removed due to the decrease in the number of address signal lines. Accordingly, the double pumped address scheme was developed.
In the double pumped address scheme, a valid command CMD and a first address ADDR1 are input at the first rising edge of a clock signal CLK and a second address ADDR2 is input at the second rising edge of the clock signal CLK, as shown in FIG. 2. In addition, a valid command is input at the first rising edge of the clock signal CLK and an invalid command is input at the second rising edge of the clock signal CLK. The 12 address signals A0 through A11 are divided into two groups and respectively set to the first address ADDR1 and the second address ADDR2. For example, the 6 address signals A0 through A5 are set to the first address ADDR1 and the 6 address signals A6 through A11 are set to the second address ADDR2.
FIG. 3 is a block diagram of a conventional double pumped address scheme memory device 300. Referring to FIG. 3, the memory device 300 includes a clock buffer 310, an address buffer 320, a command buffer 330, and an address latch circuit 340.
The clock buffer 310 receives an external clock signal CLK and generates a first internal clock signal CLK1. The address buffer 320 receives address signals ADDRs in response to the first internal clock signal CLK1 and outputs first and second internal address signals TAFi and TASi. The command buffer 330 receives command signals CMD in response to the internal clock signal CLK1 and generates a second internal clock signal PCLKD and internal command signals TCAS/TRAS/TCS/TWE. The address latch circuit 340 receives the internal command signals TCAS/TRAS/TCS/TWE and the first and second internal address signals TAFi and TASi in response to the second internal clock signal PCLKD and generates a row address RAi and a column address CAi.
FIG. 4 is a block diagram of the address buffer 320. Referring to FIG. 4, the address buffer 320 includes an input buffer 410 receiving the address signals ADDRs, an input sampler 420 sampling the output signal of the input buffer 410 in response to the first internal clock signal CLK1 and generating a clocked address signal C_ADDR, a delay 430 delaying the first internal clock signal CLK1, and a flip-flop 440 receiving the clocked address signal C_ADDR in response to the delayed first internal clock signal CLK1_D. The output signal of the input sampler 420 corresponds to the second internal address signal TAFi and the output signal of the flip-flop 440 corresponds to the first internal address signal TAFi.
FIG. 5 is a block diagram of the command buffer 330 and the address latch circuit 340. Referring to FIG. 5, the command buffer 330 includes an input buffer 510 receiving the command signal CMD, an input sampler 520 sampling the output signal of the input buffer 510 in response to the first internal clock signal CLK1, a first delay 530 delaying the first internal clock signal CLK1, a second delay delaying the first internal clock signal CLK1 to generate the second internal clock signal PCLKD, and a flip-flop 550 receiving the output signal of the input sampler 520 in response to the delayed first internal clock signal CLK1_D and generating the internal command signals TCAS/TRAS/TCS/TWE.
The address latch circuit 340 includes a command decoder 560 decoding the internal command signals TCAS/TRAS/TCS/TWE in response to the second internal clock signal CLK2 and generating a decoded command signal D_CMD, an address decoder 570 receiving the first and second internal address signals TAFi and TASi and generating decoded first and second internal address signals D_TAFi and D_TASi in response to the second internal clock signal PCLKD, and a latch 580 receiving the decoded first and second internal address signals D_TAFi and D_TASi and generating the row address RAi and column address CAi in response to the decoded command signal D_CMD.
FIG. 6 is a timing diagram for explaining the operation of the memory device 300 of FIG. 3. Referring to FIG. 3, the command signal CMD and a first address signal AF1 are input at the first rising edge C1 of the external clock signal CLK and a second address signal AS1 is input at the second rising edge C2. The internal command signal and the first and second internal address signals TAFi and TASi are generated at the third rising edge C3 of the external clock signal CLK. The second internal clock signal PCLKD is generated being delayed from the external clock signal CLK by a predetermined time. The decoded first and second internal address signals D_TAFi and D_TASi are generated in response to the internal clock signal PCLKD, and the decoded command signal D_CMD is generated. The decoded first and second internal address signals D_TAFi and D_TASi are latched in response to the decoded command signal D_CMD and the row address RAi and the column address CAi are generated.
The row address RAi and the column address CAi can be stably generated only when the decoded command signal D_CMD is generated within the window of the decoded first and second internal address signals D_TAFi and D_TASi. As shown in FIG. 6, the valid address window of the decoded first and second internal address signals D_TAFi and D_TASi corresponds to one clock cycle of the external clock signal CLK.
However, the first and second internal address signals TAFi and TASi input to the address decoder 570 have a skew between them in order to generate the decoded first and second internal address signals D_TAFi and D_TASi. Furthermore, the valid address window of the decoded first and second internal address signals D_TAFi and D_TASi becomes narrower as the operating frequency of the memory device 300 increases. Accordingly, a margin between the first and second internal address signals D_TAFi and D_TASi and the decoded command signal D_CMD is insufficient.